The innovation consists of a new domain-specific hardware description language and corresponding toolset. The language offers the possibility of describing a design at the register-transfer level (RTL) at various degrees of precision. The toolset consists of data-flow analysis of the code, conversion to an internal format and code generators for C and VHDL from this internal format.
The innovation offers rapid prototyping of hardware designs. The C-code generator in the toolset is used to create efficient simulations for the purpose of performance evaluation. The higher simulation speeds create the opportunity of more intensive design-space exploration including the refinement from floating point to fixed-point descriptions and the determination of the clock cycles in which a computation is performed. Once the design has been sufficiently defined, no recoding of the design is necessary: the VHDL-code generator provides the path to FPGA or ASIC synthesis.
The newly proposed design language is domain specific. This means that it does not suffer of the \\\\\\\\\\\\\\\"subset problem\\\\\\\\\\\\\\\" (the fact that a designer has to stick to a language subset and is obliged to follow a coding style) that occurs when an existing programming language like C is used for hardware design. Still, C (clock-cycle-true and bit-true, if desired) and VHDL can be generated for easy integration with other design tools. It is not difficult to add code generators for other target languages.
| Innovation | 2010031282 |
| Date posted | 12-03-2010 |
| Last modified | 04-02-2012 |
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